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Preliminary
RT9210
Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination
General Description
The RT9210 is a dual high power, high efficiency synchronous buck DC-DC controller optimized for high performance double data rate (DDR) memory applications. It is designed to convert voltage supplies ranging from 4.5V to 5.5V into efficiently 2.5VDDQ for powering DDR memory, VTT for signal termination and a buffered amplifier for VREF reference. VTT tracks (VDDQ/2) to 30mV, and VTT accurately tracks VREF. The RT9210 integrates all of the control, output adjustment, monitoring and protection functions into a single package. The VTT supply can be turned off independently of VDDQ during S3 sleep mode, the VTT output is maintained by a low power window regulator when V2_SD pin being triggered high. The RT9210 provides simple, single feedback loop, voltage mode control with fast transient response for VDDQ regulator. The VTT regulator features internal compensation that eases the circuitry design. It includes two phaselocked 300kHz sawtooth-wave oscillators which are placed 90 to minimize interference between the two PWM regulators. The RT9210 protects against over-current conditions by inhibiting PWM operation. It also monitors the current in the VDDQ regulator by using the RDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor.
Features
Operating with Single 5V Supply Voltage High Power VDDQ, VTT and VREF for DDR Memory VTT Tracks (VDDQ/2) to 30mV VTT Regulator Internally Compensated Support "S3" Sleep Mode Drives All Low Cost N-MOSFETs Voltage Mode PWM Control 300kHz Fixed Frequency Oscillator Fast Transient Response : Full 0% to 100% Duty Ratio Internal Soft-Start Adaptive Non-Overlapping Gate Driver Over-Current Fault Monitor on VCC, No Current Sense Resistor Required RoHS Compliant and 100% Lead (Pb)-Free
Applications
DDR Memory Termination Supply SSTL_2 and SSTL_3 Interfaces Graph Card, Motherboard, Desktop Servers High Power Tracking DC-DC Regulators
Pin Configurations
(TOP VIEW)
UGATE1 BOOT1 PHASE1 VREF FB1 COMP1 SENSE1 VREF_IN GNDA NC BOOT2 UGATE2 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PGND1 LGATE1 PVCC1 OCSET/SD V2_SD PGOOD NC SENSE2 NC VCC LGATE2 PGND2
Ordering Information
RT9210 Package Type C : TSSOP-24 S : SOP-24 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Note :
TSSOP-24 & SOP-24
RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. DS9210-05 March 2007 www.richtek.com 1
RT9210
Typical AppIication Circuit
VIN 2.5V/3.3V/5V
Preliminary
VCC 5V VIN (>VDDQ)
+
R1 3.48k
C1 1nF
C2 1uF
R6 10k
D1 1N4148 C9 0.1uF
C10 470uF
2.5V/3.3V/5V
RT9210
RESET Q5 15 21 7 VTT_SD VREF_IN C3 100pF C4 0.1uF C6 VREF_OUT 100pF C5 5.6nF R4 6.34k 20 8 4 VCC OCSET/SD SENSE1 V2_SD VREF_IN VREF PGOOD BOOT1 19 2
PHKD6N02LT Q1 1uH C12 to C15 L1 150uF (x 4)
+
VDDQ
1.8V
6 COMP1
UGATE1 1 3 PHASE1 22 PVCC1 23 LGATE1 24 PGND1 BOOT2 UGATE2 PHASE2 11 12 10 14 13
Q2
D2 1N4148 C11 0.1uF
VCC 5V
PHKD6N02LT Q3 1uH C16 to C17 L2 150uF (x 2)
+
5
C7 0.1uF R2 1k R3 1.25k C8 15nF R5 100
FB1
LGATE2 PGND2
SENSE2 17 GNDA 9
VTT 0.9V
Q4
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Preliminary Functional Pin Description
UGATE1 (Pin 1) VDDQ upper gate driver output. Connect to gate of the highside power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. BOOT1 (Pin 2) Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BOOT1 pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. PHASE1 (Pin 3) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. PHASE1 is used to monitor the voltage drop across the upper MOSFET of the VDDQ regulator for over-current protection. VREF (Pin 4) Buffered internal reference voltage of VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and DDR memory. FB1 (Pin 5) VDDQ feedback voltage. This pin is the inverting input of the error amplifier. FB1 senses the VDDQ through an external resistor divider network. COMP1 (Pin 6) VDDQ external compensation. This pin internally connects to the output of the error amplifier and input of the PWM comparator. Use a RC + C network at this pin to compensate the feedback loop to provide optimum transient response. SENSE1 (Pin 7) This pin is connected directly to the regulated output of VDDQ supply. This pin is also used as an input to create the voltage at VREF. VREF_IN (Pin 8)
RT9210
This pin is used as an option to overdrive the internal resistor divider network that sets the voltage for both VREF and the reference voltage for the VTT supply. A 100pF capacitor between VREF_IN and ground is recommended for proper operation. GNDA (Pin 9) Signal ground for the IC. All voltage levels are measured with respect to this pin. Ties the pin directly to ground plane with the lowest impedance. BOOT2 (Pin 11) Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BOOT2 pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. UGATE2 (Pin 12) VTT upper gate driver output. Connect to gate of the highside power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. PGND2 (Pin 13) Return pin for high currents flowing in low-side power N-MOSFET. Ties the pin directly to the low-side MOSFET source and ground plane with the lowest impedance. LGATE2 (Pin 14) VTT lower gate driver output. Connect to gate of the lowside power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. VCC (Pin 15) Connect this pin to a well-decoupled 5V bias supply. It is also the positive supply for the lower gate driver, LGATE2.
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RT9210
NC (Pin 10 , 16 , 18) No internal connection. SENSE2 (Pin 17)
Preliminary
LGATE1 (Pin 23) VDDQ lower gate drive output. Connect to gate of the lowside power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. PGND1 (Pin 24) Return pin for high currents flowing in low-side power N-MOSFET. Ties the pin directly to the low-side MOSFET source and ground plane with the lowest impedance.
This pin is connected directly to the regulated output of VTT supply. This pin is also used as the feedback pin of the VTT regulator and as the regulation point for the window regulator that is enable in V2_SD mode. PGOOD (Pin 19) PGOOD is an open-drain output used to indicate that both the VDDQ and VTT regulators are within normal operating voltage ranges. V2_SD (Pin 20) A TTL compatible high level at this pin puts the VTT controller into"sleep"mode. In sleep mode, both UGATE2 and LGATE2 are driven low, effectively floating the VTT supply. While the VTT supply "floats", it is held to about 50% of VDDQ via a low current window regulator which drivers VTT via the SENSE2 pin. The window regulator can overcome up to at least 10mA of leakage on VTT. While V2_SD is high, PGOOD is low. OCSET/SD (Pin 21) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET of the VDDQ regulator sets the overcurrent trip point. ROCSET, an internal 40A current source , and the upper MOSFET on-resistance, RDS(ON), set the VDDQ converter over-current trip point (IOCSET) according to the following equation:
I OCSET = 40uA x R OCSET
R DS(ON) of the upper MOSFET
An over-current trip cycles the soft-start function. Pulling the pin to ground resets the device and all external MOSFETs are turned off allowing the two output voltage power rails to float. PVCC1 (Pin 22) Connect this pin to a well-decoupled 5V supply. It is also the positive supply for the lower gate driver, LGATE1.
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Preliminary Function Block Diagram
RT9210
VCC 137.5% 0.8V Ref. 0.8V FB1 62.5% OVP & UVP OV UV Power On Reset POR
Bias OC
Thermal SHDN 40uA OCSET/SD
SoftStart 1 BOOT1 + OC OV UV Thermal SHDN Control Logic PWM1 UGATE1 PHASE1 PVCC1 LGATE1 PGND1 300kHz Oscillator + OC 90 deg OV UV shift Thermal SHDN Control Logic VCC UGATE2 BOOT2 PWM2 PGND2 LGATE2
PGOOD
Power Good
++ EA -
COMP1
VREE_IN SENSE1
SENSE2 Window Regulator V2_SD
DS9210-05 March 2007
+
VREF
200k
200k
Zf
FB2
+ EA Zc
GNDA
+ -
-
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RT9210
Absolute Maximum Ratings
Preliminary
(Note 1)
Supply Voltage, VCC -------------------------------------------------------------------------------------------------- 7V BOOT, VBOOT - VPHASE ------------------------------------------------------------------------------------------------ 7V Input, Output or I/O Voltage ----------------------------------------------------------------------------------------- GND-0.3V to 7V Package Thermal Resistance TSSOP-24, JA --------------------------------------------------------------------------------------------------------- 100C/W SOP-24, JA ------------------------------------------------------------------------------------------------------------ 90C/W Junction Temperature ------------------------------------------------------------------------------------------------- 150C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260C Storage Temperature Range ---------------------------------------------------------------------------------------- -65C to 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC -------------------------------------------------------------------------------------------------- 5V 5% Ambient Temperature Range ---------------------------------------------------------------------------------------- 0C to 70C Junction Temperature Range ---------------------------------------------------------------------------------------- 0C to 125C
Electrical Characteristics
(VCC = 5V, TA = 25C, unless otherwise specified)
Parameter VCC Supply Current Nominal Supply Current Shutdown Supply Power-On Reset POR Threshold Hysteresis Reference Voltage (V2 Error Amp Reference) V1 Error Amp Reference Voltage Tolerance Error Amp Reference Oscillator Free Running Frequency Ramp Amplitude Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate
Symbol
Test Conditions
Min
Typ
Max
Units
ICC ICCSD
OCSET/SD = VCC, UGATE1 & 2 LGATE1 & 2 Open OCSET/SD = 0V
--3.7 --
5 3 4.1 0.5
--4.5 --
mA mA V V % Sense1 % V
VCCRTH VOCSET/SD = 4.5V, VCC Rising VCCHYS VOCSET/SD = 4.5V
Reference (for V1 and V2 Error Amp) VREF2 V1EAR VREF fOSC VOSC VCC = 5V VCC = 5V Sense1 = 2.5V 49.0 -0.784 50.0 -0.8 51.0 2 0.816
275 ---
300 1.9 90 10 6
325 -----
kHz VP-P dB MHz V/s
GBW SR COMP = 10pF
---
To be continued
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Preliminary
Parameter Window Regulator Load Current Output Voltage Error PWM Controller Gate Drivers Upper Gate Source (UGATE1 and 2) Upper Gate Sink (UGATE1 and 2) Lower Gate Source (LGATE1 and 2) Lower Gate Sink (LGATE1 and 2) RUGATE RUGATE RLGATE RLGATE BOOT = 10V BOOT - VUGATE = 1V VUGATE = 1V VCC - VLGATE = 1V VLGATE = 1V ---------125 -34 -VIL VIH TSS VPGOOD+ FB1 & Sense2 Rising VPGOOD- FB1 & Sense2 Rising Shutdown Enable -2.0 -110 80 7 5 4 2 70 50 50 32 -137.5 62.5 40 320 --4 115 85 ILOAD VOUT V2_SD = VCC, 10mA load on V2 --10 7 Symbol Test Conditions Min Typ
RT9210
Max Units
---
mA %
--------100 -75 46 540 0.2 --120 90
ns ns ns ns ns % % A ns V ms % %
Upper Gate Rising Time (UGATE1 and 2) TR_UGATE CLoad = 3.3nF Upper Gate Falling Time (UGATE1 and 2) TF_UGATE CLoad = 3.3nF Lower Gate Rising Time (LGATE1 and 2) TR_LGATE CLoad = 3.3nF Lower Gate Falling Time (LGATE1 and 2) TF_LGATE CLoad = 3.3nF Dead Time Protection FB1 Over-Voltage Trip FB1 Under-Voltage Trip OCSET/SD Current Source OCP Blocking Time OCSET/SD Logic-Low Voltage Logic-High Voltage FB1OVT FB1 Rising FB1UVT FB1 Falling IOCSET VOCSET/ SD = 4.5V TDT
Soft-Start Interval Power Good Upper Threshold Lower Threshold
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions.
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RT9210
POR ( Start Up)
Preliminary
Typical Operating Characteristics
OCSET/SD ( Start Up)
Vocset/sd VCC
5V/Div
VDDQ VTT
VDDQ VTT
1V/Div
1V/Div
Time (5ms/Div)
Time (5ms/Div)
Power Good Rising
5V/Div
Power Good Falling
VCC
5V/Div
VCC
5V/Div
5V/Div
PGOOD
2V/Div
PGOOD
2V/Div
VDDQ VDDQ Time (5ms/Div) Time (5ms/Div)
Power On
IDDQ = ITT = 5A 1V/Div VDDQ 1V/Div VCC VTT 500mV/Div
Power Off
IDDQ = 10A, ITT = 5A VCC
2V/Div
1V/Div
VDDQ
5V/Div
UGATE1
VTT
10V/Div Time (5ms/Div)
UGATE
Time (200s/Div) DS9210-05 March 2007
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Preliminary
RT9210
LGATE Phase Shift
UGATE Phase Shift
5V/Div 5V/Div
UGATE1
LGATE1
5V/Div 5V/Div
UGATE2
LGATE2
Time (1s/Div)
Time (1s/Div)
VTT Sleep Mode
5V/Div
VTT Return from Sleep Mode
5V/Div
Vvs_sd
2V/Div 2V/Div
Vvs_sd
2V/Div
VDDQ VTT
20mV/Div
VDDQ VTT
5V/Div
20mV/Div
5V/Div
UGATE2
UGATE2
Time (5s/Div)
Time (5s/Div)
VDDQ Short
VTT Short
500mV/Div
VDDQ VFB1
1V/Div 500mV/Div
VTT
500mV/Div
VFB1
10V/Div
10V/Div
UGATE1
UGATE2 Time (10ms/Div) www.richtek.com 9
Time (10ms/Div) DS9210-05 March 2007
RT9210
VDDQ Transient
Preliminary
VTT Transient
50mV/Div
VDDQ
50mV/Div
50mV/Div
VDDQ
VTT
50mV/Div
VTT
5A/Div 5A/Div
IDDQ
VIN = 5V, VDDQ = 2.5V, COUT = 2000F
ITT
VIN = 5V, VTT = 1.25V, COUT = 2000F
Time (250s/Div)
Time (250s/Div)
VTT Sink & Source
VDDQ
100mV/Div
IOCSET vs. Temperature
55
50
100mV/Div
VTT
COUT = 2000F VIN = 5V,
I OCSET ( A)
5A/Div
45
40
ITT
VDDQ = 2.5V, VTT = 1.25V
35
30
Time (100s/Div)
-40
-10
20
50
80
110
140
Temperature (C)
Reference Voltage vs. Temperature
0.802 0.801 0.8
350 300
Frequency vs. Temperature
Reference Voltage (V)
Frequency (kHz)1
-40 -10 20 50 80 110 140
0.799 0.798 0.797 0.796 0.795 0.794 0.793 0.792 0.791
250 200 150 100 50 -40 -10 20 50 80 110 140
Temperature (C)
Temperature (C)
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DS9210-05 March 2007
Preliminary
RT9210
POR vs. Temperature
4.4 4.2 4
Rising
POR (V)
3.8 3.6 3.4 3.2 3 -40 -10 20 50 80 110 140
Falling
Temperature (C)
DS9210-05 March 2007
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RT9210
Applications Information
Inductor
Preliminary
The inductor is required to supply constant current to the output load. The inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. A larger value of inductance reduces ripple current and voltage. However, the larger value of inductance has a larger physical size, lower output capacitor and slower transient response time. A good rule for determining the inductance is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum output current. The inductance value can be calculated by the following equation : (VIN - VOUT) x VOUT L= VIN x FS x IOUT Where VIN is the input voltage, VOUT is the output voltage, FS is the switching frequency,
The response time is the time required to slew the inductor current from an initial current value to the transient current level. The inductor limit input current slew rate during the load transient. Minimizing the transient response time can minimize the output capacitance required. The response time is different for application of load and removal of load to a transient. The following equations give the approximate response time for application and removal of a transient load :
TRise =
Where
L x IOUT VIN - VOUT
TFall =
L x IOUT VOUT
TRise is the response time to the application of load, TFall is the response time to the removal of load,
IOUT is the transient load current step.
Input Capacitor The input capacitor is required to supply the AC current to the Buck converter while maintaining the DC input voltage. The capacitor should be chosen to provide acceptable ripple on the input supply lines. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current. Place the small ceramic capacitors close to the MOSFETs and between the drain of Q1/Q3 and the source of Q2/Q4. The key specifications for input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and voltage rating of 1.5 times is a conservative guideline. The RMS current rating for the input capacitor of a buck regulator should be greater than approximately 0.5 the DC load current.
IOUT is the peak-to-peak inductor ripple current.
The inductance value determines the converter's ripple current and the ripple current. The ripple voltage is calculated by the following equation :
I = (VIN - VOUT) x VOUT VIN x Fs x L
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance value raise the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the RT9210 will provide 0% to 100% duty cycle in response to a load transient.
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DS9210-05 March 2007
Preliminary
Output Capacitor The output capacitor is required to maintain the DC output voltage and supply the load transient current. The capacitor must be selected and placed carefully to yield optimal results and should be chosen to provide acceptable ripple on the output voltage. The key specification for output capacitor is its ESR. Low ESR capacitors are preferred to keep the output voltage ripple low. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. For transient response, a combination of low value, high frequency and bulk capacitors placed close to the load will be required. High frequency decoupling capacitors should be placed as close to the power pins of the load as possible. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. The capacitor value must be high enough to absorb the inductor's ripple current. The output ripple is calculated as : VOUT = IOUT x ESR Another concern is high ESR induced output voltage ripple may trigger UV or OV protections will cause IC shutdown. MOSFET The MOSFET should be selected to meet power transfer requirements is based on maximum drain-source voltage (VDS), gate-source drive voltage (VGS), maximum output current, minimum on-resistance (RDS(ON)) and thermal management. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The losses can be divided into conduction and switching losses. Conduction losses are related to the on resistance of MOSFET, and increase with the load current. Switching losses occur on each ON/OFF transition. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs.
RT9210
For the Buck converter the average inductor current is equal to the output load current. The conduction loss is defined as : PCD (high side switch) = IO2 * RDS(ON) * D PCD (low side switch) = IO2 * RDS(ON) * (1-D) The switching loss is more difficult to calculate. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turn-off delays and rise and fall times. With a linear approximation, the switching loss can be expressed as : PSW = 0.5 * VDS(OFF) * IO * (TRise + TFall) * F Where VDS(OFF) is drain to source voltage at off time, TRise is rise time, TFall is fall time, F is switching frequency. The total power dissipation in the switching MOSFET can be calculate as : PHigh Side Switch = IO2 * RDS(ON)* D + 0.5 * VDS(OFF)* IO* (TRise + TFall)* F PLow Side Switch = IO2 * RDS(ON) * (1-D) In RT9210, the VDDQ only sources current but the VTT can sink and source current. When sourcing current, the upper MOSFET supports most of the switching losses. On the contrary, the lower MOSFET supports most of the switching losses when VTT is sinking. Losses while Sourcing Current PHigh Side Switch = IO2 * RDS(ON)* D + 0.5 * VDS(OFF)* IO* (TRise + TFall)* F PLow Side Switch = IO2 * RDS(ON) * (1-D) Losses while Sinking Current PHigh Side = IO2 * RDS(ON) * D PLow Side = IO2 * RDS(ON)* (1-D) + 0.5 * VDS(OFF)* IO* (TRise + TFall)* F For input voltages of 3.3V and 5V, conduction losses often dominate switching losses. Therefore, lowering the RDS(ON) of the MOSFETs always improves efficiency.
DS9210-05 March 2007
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RT9210
Feedback Compensation
Preliminary
The output LC filter introduces a double pole,-40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The Resonant frequency of the LC filter expressed as follows :
The RT9210 is a voltage mode controller; the control loop is a single voltage feedback path including an error amplifier and PWM comparator as Figure 1 shows. In order to achieve fast transient response and accurate output regulation, a adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0dB crossing frequency. And to manipulate loop frequency response that its gain crosses over 0dB at a slope of -20dB/dec.
FP(LC) =
1 2 x LO x CO
The next step of compensation design is to calculate the ESR zero. The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor expressed as follows :
FZ(ESR) = 1 2 x CO x ESR
Vin
Lo PWM
Vout
Compensation Frequency Equations
Co ESR
The compensation network consists of the error amplifier and the impedance networks ZC and ZF as Figure 2 shows.
Zf
Zf + VREF
R2 C2 VOUT
PWM Comparator
+ -
Zc
C1
Zc
R1
VRAMP
Compensator
EA + FB1
COMP1
Figure 1
Modulator Frequency Equations
Rf
RT9210
VREF
Figure 2 FP1 = 0 FZ1 = FP1 = 1 2 x R2 x C2 1 2 x R2 (C1 // C2)
The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This transfer function is dominated by a DC gain and the output filter (LO and CO), with a double pole frequency at FLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the peakto-peak oscillator voltage VRAMP. The first step is to calculate the complex conjugate poles contributed by the LC output filter.
Figure 3 shows the DC-DC converter's gain vs. frequency. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop.
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DS9210-05 March 2007
Preliminary
High crossover frequency is desirable for fast transient response, but often jeopardize the system stability. In order to cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. In the experience, place the zero at 75% LC filter resonant frequency.Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The second pole be place at half the switching frequency.
80 80 Loop Gain 60 40 40 20 Gain (dB) 0 -20
-4040 0
RT9210
3. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. Place the output capacitors as close to the load as possible. 4. The inductor, output capacitor and the MOSFET should be as close to each other as possible. This helps to reduce the EMI radiated. 5. Place the switching MOSFET as close to the input capacitors as possible. The MOSFET gate traces to the IC must be as short, straight, and wide as possible. Use copper filled polygons on the top and bottom layers for the PHASE nodes. 6. Place the CBOOT as close as possible to the BOOT and PHASE pins. 7. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. Connect to the GND pin with a single trace, and connect this local GND trace to the output capacitor GND. 8. Minimize the leakage current paths on the OCSET/SD pin and locate the resistor as close to the OCSET/SD pin as possible because the internal current source isonly 40A. 9. In multilayer PCB, use one layer as ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point.
Compensation Gain
Modulator Gain
-6060 1H 0z 10db(vo) v
10z 0H v b c m 2100l ) d(op) vb o d(
1k 10k Feuny rqec Frequency (Hz)
10H .Kz
1Kz 0H
100k
10H 0Kz
10H .Mz
1M
Figure 3 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. 1. Even though double-sided PCB is usually sufficient for a good layout, four-layer PCB is the optimum approach to reducing the noise. Use the two internal layers as the power and GND planes, the top layer for power connections with wide, copper filled areas, and the bottom layer for the noise sensitive traces. 2. There are two sets of critical components in a DC-DC converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. The others are the small signal components that connect to sensitive nodes or supply critical bypass current and signal coupling. Make all critical component ground connections with vias to GND plane.
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RT9210
Outline Dimension
Preliminary
D L
E
E1
e
A A1 b
A2
Symbol A A1 A2 b D e E E1 L
Dimensions In Millimeters Min 0.850 0.050 0.800 0.190 7.700 0.650 6.300 4.300 0.450 6.500 4.500 0.750 Max 1.200 0.150 1.050 0.300 7.900
Dimensions In Inches Min 0.033 0.002 0.031 0.007 0.303 0.026 0.248 0.169 0.018 0.256 0.177 0.030 Max 0.047 0.006 0.041 0.012 0.311
24-Lead TSSOP Plastic Package
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DS9210-05 March 2007
Preliminary
RT9210
A
H M
J
B
F
C I D
Symbol A B C D F H I J M
Dimensions In Millimeters Min 15.189 7.391 2.362 0.330 1.194 0.229 0.102 10.008 0.381 Max 15.596 7.595 2.642 0.508 1.346 0.330 0.305 10.643 1.270
Dimensions In Inches Min 0.598 0.291 0.093 0.013 0.047 0.009 0.004 0.394 0.015 Max 0.614 0.299 0.104 0.020 0.053 0.013 0.012 0.419 0.050
24-Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
DS9210-05 March 2007
www.richtek.com 17

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